1. Technical Field
The present disclosure relates to amplifiers and in particular to audio amplifiers with asymmetric supply. The present disclosure also relates, but not exclusively, to mobile telephony.
2. Description of the Related Art
Asymmetric supply amplifiers, and in particular those equipping mobile telephones, receive a continuous supply voltage. To maximize their dynamic, these amplifiers receive a biasing voltage equal to the supply voltage divided by two. FIG. 1 schematically shows an amplification circuit. In FIG. 1, the circuit comprises an amplifier AMP comprising two inputs and one output, and supplied between voltages PV and PVN. The signal to amplify Vin is input to the first of the two inputs by the intermediary of a resistor R1. A bias voltage Vb is input to the second input of the amplifier AMP. The first input is linked to the output of the amplifier AMP by the intermediary of a resistor R2. The output of the amplification circuit supplies an amplified signal Vout corresponding to the difference between the input signal Vin and the bias voltage Vb. The voltage PVN is for example equal to 0 V or −PV and the voltage Vb is for example equal to (PV−PVN)/2.
FIG. 2 shows, in the form of diagrams, three cases of adjustment of the bias voltage Vb. In a first case, the voltage Vb is adjusted to the median voltage equal to the difference between the supply voltages PV and PVN of circuit, divided by two (that is, (PV−PVN)/2). The voltage range of the amplifier is between the voltage PVN and the voltage PV. The voltage range of the amplifier is thus at a maximum. In a second case, the bias voltage is less than the median voltage (PV−PVN)/2. In a third case, the voltage Vb is greater than the voltage (PV−PVN)/2. To avoid a saturation of the amplifier leading to a distortion of the amplified signal Vout and knowing that the amplified signal cannot be less than PVN or greater than PV, the gain of the amplifier is adjusted in a manner such that the voltage extremes of the output signal remain between PVN and PV. The voltage range of the amplifier thus varies in the second case between PVN and 2(Vb−PVN) (<PV) and in the third case, between PV−2(PV−Vb) {that is, 2 Vb−PV (>PVN)} and PV. It thus appears that to maximize the voltage range of the amplifier, the bias voltage must be maintained at the median voltage of the supply voltages, that is (PV−PVN)/2.
Nevertheless, the supply voltage of a mobile telephone coming from a battery may vary greatly, in particular due to the battery charge and the active elements of the telephone. If the bias voltage Vb follows the median voltage of the supply voltages, it results that any variation of the voltage Vb is transmitted on output of the amplifier AMP with a gain equal to 1+R1/R2. However, the quality of an amplifier is mainly determined by the rejection ratio of the supply voltage PSRR (Power Supply Rejection Ratio), generally expressed in negative decibels (dB). The weaker the ratio PSRR (absolute value) of a circuit, the less the circuit is sensitive to supply voltage variations. The amplification circuit of FIG. 1 has a negative ratio PSRR of several dB. In the case where the gain of this circuit is equal to 1, the ratio PSRR is equal to −6 dB.
FIG. 3 shows a differential amplification circuit. In FIG. 3, the amplification circuit comprises a differential amplifier DAMP comprising three inputs and two outputs, and supplied between the voltages PV and PVN. The input signal Vin is supplied between two of the inputs by the intermediary of resistors R1, R1′, and the bias voltage Vb is supplied to a third input. The input connected to the resistor R1 is linked to one output by the intermediary of a resistor R2. The input connected to the resistor R1′ is linked to the other output by the intermediary of a resistor R2′. The output amplified signal is supplied between the two outputs. In this circuit, the variations of the bias voltage Vb are transmitted on output of the amplifier DAMP with an attenuation varying as a function of the matching of resistors R1 and R1′ and of the matching of resistors R2 and R2′. Current technology allows a matching of resistors R1, R1′ and R2, R2′ within 0.1%. In these conditions, the ratio PSRR can reach approximately −66 dB.
To increase the rejection of the supply voltage (that is to say, to diminish the ratio PSRR) from a certain frequency, it has been envisaged to generate the bias voltage Vb from supply voltages PV and PVN, with the aid of a voltage divider and of a low-pass filter. FIG. 4 shows a generation circuit RFG1 of the bias voltage Vb, connected to the amplification circuit of FIG. 1. The generation circuit RFG1 comprises two resistors R3, R4 and a capacitor C1. The two resistors R3, R4, are connected in series between the terminals to voltages PV and PVN of a voltage supply source, and have for example identical values so as to form a voltage divider by two. The voltage MPV at a junction node N1 between resistors R3, R4 is therefore substantially equal to the median voltage of supply voltages PV, PVN {that is, (PV−PVN)/2}, with a small difference depending on the matching of resistors R3 and R4. The voltage MPV at node N1 is filtered with the aid of a low-pass RC filter formed by the resistor R4 and the capacitor C1 connected between the node N1 and ground. The node N1 supplies the bias voltage Vb to the amplifier AMP. The ratio PSRR obtained is low at frequencies greater than the cut-off frequency of the low pass filter. It is therefore advantageous that the cut-off frequency of the filter is low. To this end, the greater the capacitance of the capacitor C1 and/or the value of the resistor R4, the weaker the cut-off frequency of the filter. Nevertheless, if it is desired to make the amplification circuit in an integrated circuit, it is not possible to form a high capacitance capacitor, unless a capacitor external to the integrated circuit is used.
To overcome this problem, it has been proposed, in particular in U.S. Pat. No. 6,696,884, to insert a controlled interrupter I1 between the node N1 and the capacitor C1, so as to form a sample and hold circuit. The interrupter is for example formed by a CMOS transistor, and controlled in a manner so as to open and close according to a certain sampling frequency. This disposition allows the ratio PSRR to be decreased to frequencies less than the sampling frequency. It is therefore advantageous that the sampling frequency be low. However, the leakage current during blocked periods (interrupter I1 open) is not negligible, which causes an undulation of the bias voltage Vb. It results that the lower the sampling frequency, the higher the undulation amplitude of the voltage Vb, and thus the more the ratio PSRR increases.
It may therefore be desired to make an amplifier that may be entirely integrated, and has a low (less than −70 dB) ratio PSRR in a large as possible useful frequency band.